1. Field of the Invention
The present invention relates to a semiconductor transistor device with a high packing density and a method for producing a miniaturized semiconductor transistor device capable of high speed operation.
2. Description of the Prior Art
A semiconductor transistor device having a high packing density such as an LSI has recently been developed to have a smaller element size. Such a development has brought problems such as the decreasing of a withstand voltage of transistors and an instability of an inversion threshold voltage of transistors.
Referring to the attached drawings, a production method for a conventional metal-oxide-semiconductor type field effect transistor (MOS transistor) will now be described. FIGS. 14A through 14D show an example of the production method of a conventional n-channel type MOS transistor.
As is shown in FIG. 14A, boron ions are implanted into a p-type semiconductor substrate 1 to form a p.sup.+ -type semiconductor region 10, which is then oxidized to form a gate insulating film 3 with a thickness of 8 to 12 nm.
After depositing a polysilicon film with a thickness of 200 to 300 nm on a top surface of the gate insulating film 3, a polysilicon gate electrode 4 is formed through ordinary photolithography and etching processes as is shown in FIG. 14B. Next, phosphorus ions are implanted into the substrate 1 by an ion implantation using the gate electrode 4 as a mask, thereby forming n.sup.- -type semiconductor regions (LDD regions) 6a and 6b as part of a source region and part of a drain region, respectively.
A silicon oxide film is deposited on the top surface of the patterned substrate 1, and then main portions of the deposited film are removed by an anisotropic dry etching so as to allow side wall spacers 5a and 5b to remain on side walls of the gate electrode 4 as is shown in FIG. 14C. Then arsenic ions are implanted by the ion implantation using the gate electrode 4 and the side wall spacers 5a and 5b as a mask, thereby forming n.sup.+ -type semiconductor regions 7a and 7b, which are parts of the source region and the drain region, respectively. Next, the substrate 1 is heat treated at 900.degree. C. for 30 minutes in order to activate the arsenic ions in the n.sup.+ -type source and drain regions 7a and 7b and repair crystal defects (lattice damages).
An interlevel insulating film 11 is deposited in an ordinary manner as is shown in FIG. 14D. After etching contact portions in the interlevel insulating film 11 to form contact holes, metal electrodes 12a and 12b are formed to contact with the n.sup.+ -type source and regions 7a and 7b.
An operation of the n-channel type MOS transistor with the above-mentioned structure will now be described. The p+-type semiconductor region 10 serves to prevent a punch through effect, that is, an effect in which a drain depletion layer of the transistor is extended and the withstand voltage is decreased. In addition, an impurity concentration of the p.sup.+ -type semiconductor region 10 determines the inversion threshold voltage of the MOS transistor. The n.sup.- -type LDD regions 6a and 6b serve to decrease the strength of electric fields near the source and drain regions so as to prevent the MOS transistor from degrading due to a hot carrier injection.
Alternatively, a similar result can be attained by increasing an impurity concentration of the p-type semiconductor substrate 1 or using a p-type well with a high impurity concentration instead of forming the p.sup.+ -type semiconductor region 10 in the device of FIGS. 14A through 14D. However, in such a device having an increased p-type impurity concentration, there are some problems to prevent attaining a miniaturization and a high speed operation of the MOS transistor.
The conventional MOS transistor, in which the p.sup.+ -type semiconductor region 10 controls the inversion threshold voltage and increases a voltage at which the punch through is caused (hereinafter called the "punch through withstand voltage") has the following problems:
1. The junction capacitance is increased due to a high impurity concentration near pn-junctions of the source region and the drain region. Such a large junction capacitance makes it difficult to operate a circuit at a high speed.
2. When the impurity concentration of the p.sup.+ -type semiconductor region 10 is increased to prevent the punch through, the inversion threshold voltage is inevitably increased and the drivability (transconductance) of the MOS transistor is decreased. In other words, it is difficult to get satisfactory values for all of the punch through withstand voltage, the inversion threshold voltage and the drivability.
3. A substrate bias effect in which the electrical characteristic of the MOS transistor depends upon an electrical potential of the substrate 1 is reinforced by the existence of the p.sup.+ -type semiconductor region 10.
4. Since a heat treatment at a high temperature such as 900.degree. C. or more must be conducted in order to activate the impurities after forming the n.sup.+ -type source and drain regions, a short channel effect is reinforced because the n.sup.- -type LDD region is diffused and an effective channel length of the transistor is decreased.